ChongMing Group (HK) Int'l Co., Ltd

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CDCVF2310PWR Clock Timer ICS Clock Buffer HP 1:10 Clock Buffer 10 Output

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Country/Region:china
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CDCVF2310PWR Clock Timer ICS Clock Buffer HP 1:10 Clock Buffer 10 Output

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Brand Name :Ti
Model Number :CDCVF2310PWR
MOQ :Contact us
Price :Contact us
Payment Terms :Paypal, Western Union, TT
Supply Ability :50000 Pieces per Day
Delivery Time :The goods will be shipped within 3 days once received fund
Packaging Details :TSSOP24
Description :Clock Fanout Buffer (Distribution) IC 1:10 200 MHz 24-TSSOP (0.173", 4.40mm Width)
Supply Voltage - Min :2.3 V
Supply Voltage - Max :3.6 V
Minimum Operating Temperature :- 40 C
Maximum Operating Temperature :+ 85 C
Number of Outputs :10 Output
Maximum Input Frequency :200 MHz
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CDCVF2310PWR Clock Timer ICS Clock Buffer HP 1:10 Clock Buffer

1 Features

  • High-Performance 1:10 Clock Driver
  • Operates up to 200 MHz at VDD 3.3 V

  • Pin-to-Pin Skew < 100 ps at VDD 3.3 V

  • VDD Range: 2.3 V to 3.6 V

  • Operating Temperature Range –40°C to 105°C

  • Supports 105oC Ambient Temperature (see Thermal Considerations)

  • Output Enable Glitch Suppression

  • Distributes One Clock Input to Two Banks of Five Outputs

  • 25-Ω On-Chip Series Damping Resistors

  • Packaged in 24-Pin TSSOP

2 Applications

• General-Purpose Applications

3 Description

The CDCVF2310 device is a high-performance, low- skew clock buffer that operates up to 200 MHz. Two banks of five outputs each provide low-skew copies of CLK. After power up, the default state of the outputs is low regardless of the state of the control pins. For normal operation, the outputs of bank 1Y[0:4] or 2Y[0:4] can be placed in a low state when the control pins (1G or 2G, respectively) are held low and a negative clock edge is detected on the CLK input. The outputs of bank 1Y[0:4] or 2Y[0:4] can be switched into the buffer mode when the control pins (1G and 2G) are held high and a negative clock edge is detected on the CLK input. The device operates in a 2.5-V and 3.3-V environment. The built-in output enable glitch suppression ensures a synchronized output enable sequence to distribute full period clock signals.

The CDCVF2310 is characterized for operation from –40°C to 85°C.

Device Information

PART NUMBER

PACKAGE

BODY SIZE (NOM)

CDCVF2310

TSSOP (24)

4.40 mm × 7.80 mm

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