ChongMing Group (HK) Int'l Co., Ltd

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Hex Non - Inverting Buffers HEF4050BT,653 Integrated Circuit Chip Electronics Ic Chip

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Country/Region:china
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Hex Non - Inverting Buffers HEF4050BT,653 Integrated Circuit Chip Electronics Ic Chip

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Model Number :HEF4050BT
Certification :new & original
Place of Origin :original factory
MOQ :10pcs
Price :negotiation
Payment Terms :T/T, Western Union, PayPal
Supply Ability :300pcs
Delivery Time :1 day
Packaging Details :please contact me for details
Description :Buffer, Non-Inverting 6 Element 1 Bit per Element Push-Pull Output 16-SO
feature 1 :Accepts input voltages in excess of the supply voltage
feature 2 :Fully static operation
feature 3 :5 V, 10 V, and 15 V parametric ratings
feature 4 :Standardized symmetrical output characteristics
feature 5 :Operates across the full industrial temperature range −40 °C to +85 °C
feature 6 :Complies with JEDEC standard JESD 13-B
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General description

The HEF4050B provides six non-inverting buffers with high current output capability

suitable for driving TTL or high capacitive loads. Since input voltages in excess of the

buffers’ supply voltage are permitted, the buffers may also be used to convert logic levels

of up to 15 V to standard TTL levels.

It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS

(usually ground). Unused inputs must be connected to VDD, VSS, or another input. It is

also suitable for use over the industrial (−40 °C to +85 °C) temperature range.

Features

■ Accepts input voltages in excess of the supply voltage

■ Fully static operation

■ 5 V, 10 V, and 15 V parametric ratings

■ Standardized symmetrical output characteristics

■ Operates across the full industrial temperature range −40 °C to +85 °C

■ Complies with JEDEC standard JESD 13-B

■ ESD protection:

◆ HBM JESD22-A114E exceeds 2000 V

◆ MM JESD22-A115-A exceeds 200 V

Applications

■ LOCMOS (Local Oxidation CMOS) to DTL/TTL converter

■ HIGH sink current for driving two TTL loads

■ HIGH-to-LOW level logic conversion

Functional diagram

Pinning information

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