ChongMing Group (HK) Int'l Co., Ltd
CHONGMING GROUP (HK) INT'L CO., LTD.
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TUSB3410 USB TO SERIAL PORT CONTROLLER
1.Controller Description
The TUSB3410 provides bridging between a USB port and an enhanced UART serial port. The TUSB3410 contains all the necessary logic to communicate with the host computer using the USB bus. It contains an 8052 microcontroller unit (MCU) with 16K bytes of RAM that can be loaded from the host or from external on-board memory via an I2C bus. It also contains 10K bytes of ROM that allow the MCU to configure the USB port at boot time. The ROM code also contains an I2C boot loader. All the device functions such as the USB command decoding, UART setup, and error reporting are managed by the internal MCU firmware under the auspices of the PC host.
The TUSB3410 can be used to build an interface between a legacy serial peripheral device and a PC with USB ports, such as a legacy-free PC. Once configured, data flows from the host to the TUSB3410 via USB OUT commands and then out from the TUSB3410 on the SOUT line. Conversely, data flows into the TUSB3410 on the SIN line and then into the host via USB IN commands.
Figure 1–1. Data Flow
Figure 1–2. USB-to-Serial (Single Channel) Controller Block Diagram
2. Main Features
2.1 USB Features
• Fully compliant with USB 2.0 full speed Specifications
• Supports 12-Mbps USB data rate (full speed)
• Supports USB suspend, resume, and remote wakeup operations
• Supports two power source modes:
– Bus-powered mode
– Self-powered mode
• Can support a total of 3-input and 3-output (interrupt, bulk) endpoints
2.2 General Features
• Integrated 8052 microcontroller with
– 256 × 8 RAM for internal data
– 10K × 8 ROM (with USB and I2C boot loader)
– 16K × 8 RAM for code space loadable from host or I2C port
– 2K × 8 Shared RAM used for data buffers and endpoint descriptor blocks (EDB)
– Four GPIO pins from 8052 port 3
– Master I2C controller for EEPROM device access
– MCU operates at 24 MHz providing 2 MIPS operation
– 128-ms Watchdog Timer
• Built-in two-channel DMA controller for USB/UART bulk I/O
• Operates from a 12-MHz crystal
• Supports USB suspend and resume
• Supports remote wake-up
• Available in 32-pin LQFP
• 3.3-V operation with 1.8-V core operating voltage provided by on-chip 1.8-V voltage regulator
2.3 Enhanced UART Features
• Software/hardware flow control:
– Programmable Xon/Xoff characters
– Programmable Auto-RTS/DTR and Auto-CTS/DSR
• Automatic RS485-bus transceiver control, with and without echo
• Selectable IrDA mode for up to 115.2 kbps transfer
• Software selectable baud rate from 50 to 921.6 k baud
• Programmable serial-interface characteristics
– 5-, 6-, 7-, or 8-Bit characters
– Even, odd, or no parity-bit generation and detection
– 1-, 1.5-, or 2-Stop bit generation
• Line break generation and detection 2–2
• Internal test and loop-back capabilities
• Modem-control functions (CTS, RTS, DSR, DTR, RI, and DCD)
• Internal diagnostics capability
– Loopback control for communications link-fault isolation
– Break, parity, overrun, framing-error simulation
2.4 Pinout Information
Table 2–1. Terminal Functions
| TERMINAL | I/O | DESCRIPTION | |
| NAME | NO. | ||
| CLKOUT | 22 | O | Clock output (controlled by CLKOUTEN and CLKSLCT in MODECNFG register (see Section 5.1.5 and Note 1) |
| CTS | 13 | I | UART: Clear to send (see Note 4) |
| DCD | 15 | I | UART: Data carrier detect (see Note 4) |
| DM | 7 | I/O | Upstream USB port differential data minus |
| DP | 6 | I/O | Upstream USB port differential data plus |
| DSR | 14 | I | UART: Data set ready (see Note 4) |
| DTR | 21 | O | UART: Data terminal ready (see Note 1) |
| GND | 8, 18, 28 | GND | Digital ground |
| P3.0 | 32 | I/O | Port-3.0 (see Notes 3, 4, 5, and 8) |
| P3.1 | 31 | I/O | Port-3.1 (see Notes 3, 4, 5, and 8) |
| P3.3 | 30 | I/O | Port-3.3 (see Notes 3, 4, 5, and 8) |
| P3.4 | 29 | I/O | Port-3.4 (see Notes 3, 4, 5, and 8) |
| PUR | 5 | O | Pull-up resistor connection (see Note 2) |
| RESET | 9 | I | Controller master reset signal (see Note 4) |
| RI/CP | 16 | I | UART: Ring indicator (see Note 4) |
| RTS | 20 | O | UART: Request to send (see Note 1) |
| SCL | 11 | O | Master I2C controller: clock signal (see Note 1) |
| SDA | 10 | I/O | Master I2C controller: data signal (see Notes 1 and 5) |
| SIN/IR_SIN | 17 | I | UART: Serial input data / IR Serial data input (see Note 6) |
| SOUT/IR_SOUT | 19 | O | UART: Serial output data / IR Serial data output (see Note 7) |
| SUSPEND | 2 | O | Suspend condition signal (see Note 3) |
| TEST0 | 23 | I | Test input (for factory test only) (see Note 5) |
| TEST1 | 24 | I | Test input (for factory test only) (see Note 5) |
| VCC | 3, 25 | PWR | 3.3 V |
| VDD18 | 4 | PWR | 1.8-V Supply. An internal voltage regulator generates this supply voltage when terminal VREGEN is asserted. When VREGEN is deasserted, 1.8 V must be supplied externally. |
| VREGEN | 1 | I | This active-low terminal is used to enable the 3.3-V to 1.8-V voltage regulator in the core. |
| WAKEUP | 12 | I | Remote wake-up request pin. When low, wakes up system (see Note 5) |
| X1/CLKI | 27 | I | 12-MHz crystal input or clock input |
| X2 | 26 | O | 12-MHz crystal output |
NOTES:
1. 3-state CMOS output (±4-mA drive/sink)
2. 3-state CMOS output (±8-mA drive/sink)
3. 3-state CMOS output (±12-mA drive/sink)
4. TTL-compatible, hysteresis input
5. TTL-compatible, hysteresis input, with internal 100-µA active pullup
6. TTL-compatible input without hysteresis, with internal 100-µA active pullup
7. Normal or IR mode: 3-state CMOS output (±4-mA drive/sink)
8. The MCU treats the outputs as open drain types in that the output can be driven low continuously, but a high output is driven for two clock cycles and then the output is tristated.