74HC273D Integrated Circuit Chip Octal D Type Flip Flop With Reset , Positive Edge Trigger

74HC273D Integrated Circuit Chip Octal D Type Flip Flop With Reset , Positive Edge Trigger

74HC273; 74HCT273
Octal D-type flip-flop with reset; positive-edge trigger

General description
The 74HC273; 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW on MR forces the outputs LOW independently of clock and data inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V_CC.

Features and benefits

• Input levels:
  • For 74HC273: CMOS level
  • For 74HCT273: TTL level
• Common clock and master reset
• Eight positive edge-triggered D-type flip-flops
• Complies with JEDEC standard no. 7A
• ESD protection:
  • HBM JESD22-A114F exceeds 2000 V
  • MM JESD22-A115-A exceeds 200 V.
• Multiple package options
• Specified from -40 ℃ to +85 ℃ and from -40 ℃ to +125 ℃

Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V)

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For DIP20 package: above 70 ℃ the value of Ptot derates linearly with 12 mW/K.
[3] For SO20 package: above 70 ℃ the value of Ptot derates linearly with 8 mW/K.
For SSOP20 and TSSOP20 packages: above 60 ℃ the value of Ptot derates linearly with 5.5 mW/K.
For DHVQFN20 packages: Ptot derates linearly with 4.5 mW/K above 60 ℃.

Functional diagram



Pinning




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