MT48LC4M16A2TG Synchronous Dram MICRON Original Package TSOP Tray
MT48LC16M4A2 – 4 Meg x 4 x 4 banks
GENERAL DESCRIPTION
The Micron® 64Mb SDRAM is a high-speed CMOS,
dynamic random-access memory containing 67,108,864 bits.
It is internally configured as a quadbank DRAM with a synchronous interface
(all signals are registered on the positive edge of the clock signal, CLK).
Each of the x4’s 16,777,216-bit banks is organized as 4,096 rows by 1,024 columns by 4 bits.
Each of the x8’s 16,777,216-bit banks is organized as 4,096 rows by 512 columns by 8 bits.
Each of the x16’s 16,777,216- bit banks is organized as 4,096 rows by 256 columns by 16 bits.
FEATURES
• PC66-, PC100-, and PC133-compliant
• Fully synchronous; all signals registered on positive edge of system clock
• Internal pipelined operation; column address can be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst leCM GROUPhs: 1, 2, 4, 8, or full page
• Auto Precharge, includes CONCURRENT AUTO PRECHARGE, and Auto Refresh Modes
• Self Refresh Modes: standard and low power
• 64ms, 4,096-cycle refresh
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
OPTIONS MARKING
• Configurations
16 Meg x 4 (4 Meg x 4 x 4 banks) : 16M4
8 Meg x 8 (2 Meg x 8 x 4 banks) : 8M8
4 Meg x 16 (1 Meg x 16 x 4 banks) : 4M16
• WRITE Recovery (t WR)
t WR = “2 CLK”1 : A2
• Plastic Package – OCPL2
54-pin TSOP II (400 mil) : TG
• Timing (Cycle Time)
10ns @ CL = 2 (PC100) -8E 3, 4,5
7.5ns @ CL = 3 (PC133) -75
7.5ns @ CL = 2 (PC133) -7E
6ns @ CL = 3 (PC133, x16 Only) -6
• Self Refresh
Standard: None
Low Power : L
• Operating Temperature Range
Commercial (0°C to +70°C) :None
Industrial (-40°C to +85°C): IT 3
Part Number Example: MT48LC8M8A2TG-75
NOTE:
1. Refer to Micron Technical Note: TN-48-05.
2. Off-center parting line.
3. Consult Micron for availability.
4. Not recommended for new designs.
5. Shown for PC100 compatibility.
